A miniaturization and microfabrication of the semiconductor device are advanced from the former, and how to make it small without causing various trouble has been an important problem.
And in recent years, in order to solve the above-mentioned problem, the AG-AND (Assist Gate-AND) type flash memory provided with a plurality of Assist Gate's for forming an inversion layer in the main front surface side of a semiconductor substrate, a floating gate formed between these Assist Gate's, and a control gate formed on this floating gate is proposed (for example, refer to Patent Reference 1).
The manufacturing method of this AG-AND type flash memory is provided with the step which forms Assist Gate on the main front surface of a semiconductor substrate, the step which forms an insulating film so that this Assist Gate may be covered, the step which performs dry etching to this insulating film, and a sidewall is formed on the both side surfaces of Assist Gate, and exposes the main front surface of a semiconductor substrate located between sidewalls, the step which forms the tunnel insulating film of a floating gate growing up an insulating film on the main front surface of the semiconductor substrate located between these sidewalls, and the step which fills up the recess between these sidewalls with a conductive layer, and forms a floating gate.
However, in the structure of the above flash memories, it fills up with the insulating film between floating gates. For this reason, when microfabrication is advanced, the gap of floating gates becomes narrow and the capacity between floating gates increases. Hereby, when the charge quantity accumulated into the floating gate of the selected memory cell was changed on the occasion of read operation, there was a problem on which the threshold value voltage of the selected memory cell is changed of the so-called threshold value voltage Vth shift having occurred, and becoming easy to generate malfunction.
On the other hand, the technology of decreasing the capacity between wirings by forming a cavity (occluded cavity) between wirings rather than embedding an insulator thoroughly between wirings is proposed (for example, refer to Patent Reference 2).
In this Patent Reference 2, the structure which formed the cavity in the insulating film which separates a plurality of wirings formed on the semiconductor substrate is described. It is described that, after an insulating film which has a cavity between wirings so that a plurality of wirings may be covered is formed as the manufacturing method, flattening of the upper surface of the insulating film is done.
[Patent Reference 1] Japanese Unexamined Patent Publication No. 2005-085903
[Patent Reference 2] Japanese Unexamined Patent Publication No. Hei 2-86146